A Dynamic RAM testing machine
by Ralph Klimek 1987

based on the principal of the Zero Bit Computer

This machine was designed and biult by me in 1987/8 to demonstrate the Zero Bit Computer concept to myself. There was also a need in our department for the testing of 256kbit dynamic ram chips that were being used in the current generation of PC ATs. This machine permitted rapid go/ no go testing of 64k, 256k and 1Mbit dynamic rams.

Given the slow speed of microprocessors in 1987 it was unrealistic to base a dynamic ram tester on one, especially given the complex timing signals required to make a dynamic ram work. The RAS and CAS signals are also time critical. Only a hardware based sequencer has any prospect of being able to meet the timing requirements of a RAM chip. A Dynamic RAM is only dynamic in the sense that the data representation is in terms of charge stored under the gate electrode of a MOS transistor. This charge is measured in femto coulombs, that is not a lot. A dynamic RAM stores data in the charge stored in this gate capacitance. Data is retained by periodically reading all data and writing it back. The write back is done internally on the chip, the external complexity arises from the requirement to multiplex the address lines using differant sequences to determine the operating mode of the chip. Timing is critical. On writing data, the WE (write enable) signal is not a strobe or clock, it is merely a suggestion to the chip that when the correct RAS CAS sequence occurs, input data is latched internally. To retain data either a special refresh cycle is performed , a sort of dummy read, or just read everything.  Every cell must be read or refreshed every 4 milliseconds.

This machine performs 4 tests,  write /read all one, all zeroes, parity of address bits, inverse parity of address bits.  Using the parity function was a simple way of getting "random data" that was a strong function of the address, this would check that the RAM could properly decode its address bus. This fault could not be flagged by a simple ones and zeroes test.  This machine could cycle continuously where we needed a burn in function.  There is also a mechanism to test access time and this revealed interesting ram behaviour under adverse conditions.  I observed that the current generation of DRAMs  had their access times limited by ambient temperature. The hotter the DRAM got the worse the reliable access time became.  Provided that it was possible to keep a DRAM chip cold,  a chip specified for 250nS  would work reliably  at 100ns.  My automatic parametric test was performed by recording the returned data and qualifying it in  differant time windows.

The main sequencing, read write control, done with this microsequencer. Tests included a burn in test, data once written could be read forever untill error was detected and flagged.  This machine was microprogrammed by a simple map of concept/intention to wire.
microsequencer for generating chip RAS and CAS  and clock distribution. The raw RAS and CAS signals from the phase decoders are cleaned up by D flip-flops to eliminate glitches. Note the use of multiple input gates used to create arbitary digital waveforms by decoding the complete count and then just ANDing all the required unary bits.  This permits the simple generation of arbitary waveforms. RAS/CAS generation is just one such application. Never attempt to drive RAM control signals through decoded logic unless the edges are qualified by a D flip flop. You simply cannot design away the decoding glitches and clean edges are very important to RAM.

The slowed clock was supplied to the chain of 4 bit counters that generated the ram address.  At 20Mhz, these four bit counters were too slow to permit continuous clocking, so this is a semi-synchronous logic.  Four cascaded counters could generate and propagate a clean CARRY OUT signal, but five of them would produce an unuseable carry signal. This is because , sadly forthese chips, the CARRY signal had to propagate through too many internal gates in series. So, how then to generate a reliable 20 bit counter at 20Mhz ?   The clock pulse could still be 50ns but here we issue one clock pulse to the  counter clocks and wait for the CARRY signal to settle. Here we stall the main machine clock , once for each unique address to be generated, while we wait another 100ns to be sure that the counters have settled into a "believe-able" state. We would not have had this problem if this had been done with ECL !
Logical address bits  generator, nothing more than a 20 bit counter. Because of the  long carry propagation delay this counter needed a gated clock rather than run synchronously. Gated clocks break the simple synchronous paradigm but are a requirement when long multi-gate and multi-package have a long serial delay path as the counter carry signal requires. I tried to use look ahead carry but the design effort was beyond me. The master-reset signal is created by cleaning up the reset switch with a JK FF.
data for one bit wide drams was generated by getting the odd and even parity of the address bits and writing that. This gave a reasonably thorough test of the drams ability to decode its address bus.  This tester could measure access time by gating read back data at differant sample times. It revealled that 200ns drams could be run at 100ns if you kept them cold! read back data is compared in the XOR gate. The JK flip flops are clocked on various delayed clock edges and record that state of the data comparison. The SEQ counters are decoded and drive the 74180 parity generators. They had control inputs to make the 74180 generate a selection of odd parity, even parity, ONE or ZERO.   The raw readback data from the DRAM was compared with the exclusive OR gate and the data which had been written. Its state was latched in the JK flip flops whose individual clocks were derived from assorted delayed edges of the main system master clock.  The effect was to measure the time at which the data read back became valid.
logical ram addresses are mapped to physical chip addresses pins as a function of the chip type by this MUX array. A switch permitted the device-under-test to be reloaded while the machine was powered up by tristating the drivers
This is the "plain language" microprogram  for both microsequencers. This allmost directly maps to the wiring of the machines. There are two micro programs here. There is the phase sequencer that is responsible for creating the RAS and CAS dram signals and controlling the dram address mux and ensuring the setup and hold time requirement of the dram is satisfied.  The main sequence generator contains the high level program that orchestrates the complete test program. Its a direct application of the zero-bit-computer paradigm
logic that selects the right address lines to chip address lines for differant sized ram chips. Muxes are used to generate arbitary logic functions, rather than random logic. Errors in design or logic analysis are easily rectified by reallocating ones and zeroes to the mux inputs rather than completely redesigning a random logic wiring map.
assigning external human switches to their meanings and wiring on teh board
The Project as built.  The wirewrap cards came from an Burroughs mainframe that I used to maintain, a long time ago
wirewrap is really to only cost effective method for one off  projects like this.  

Did it work ?


Would you want to copy the design ? Why.  It would not be implemented like this in this day and age. Maybe one would simply
lift the circuit and plonk it into an FPGA. In any case we would look down our noses at any DRAM less than 64M bit today. When
I designed this my boss would not fork out even for one 1M bit DRAM,  too expensive !


page created...forgot when
Wed Dec  8 19:13:51 EST 2010  cleaned up formatting, added extra notes, added my "style rules"