a  rant by Ralph Klimek Aug 2007

If, as I claim, ECL was so superior, why then was it a commercial failure and neglected. (Rockefeller's Razor..."hey buster, if youre so smart how come youre not rich ?") By 1975, the TTL interface , chip sets and extentions were widely licencsed by TI and a very rich commercial offering of TTL chips and hundreds of SSI, MSI and LSI chip functions were widely available, and as I recall, were available for pocket money prices.

In contrast, in 1975 the ECL interface had not been licensed to anyone and only a small but functional library of ECL parts were available. Many SSI gates and a smattering of MSI functions. By 1980 there was offered an ECL 8 bit slice processor that should have set the minicomputer world ablaze with 100 Mip CPUs, instead minicomputer makers used heavily microprogrammed bit slice designs based on AMD's barely functional 2901 family that chugged along at a breathtaking 8Mhz to produce a machine that had maybe a mip or two. What happened ?  I really do not know the answere to this but I suspect the truth to have been a spectacular marketing failure; either that or my silly conspiracy theory is right!

Every ECL gate without exception was inherently a line driver. Every ECL gate input had effectively infinite input symetrical impedance. (ok, microamps and 2 pF !) . (unlimited fan out!) The current drawn from the power supply did not change as the logic functions changed state! All ECL outputs were inherently wire OR/AND able with no speed penalty. All conductors were to be treated as if they were transmission lines. This is one area were TI's superior marketing people got them. They called this "hard to design with" because digital people are frightened of analog things like transmission lines. It actually wasnt, we shall see. It was possible to "lego brick" ECL gates together, provided you remembered to treat all nodes as a transmission lines and sheild your clock lines!  This simple principle was alien and incomprehensible to the average TTL designer of the time. The one furphy that TI marketing put out was that ECL was power hungry. This was actually true, ECL gates eat power, and everyone knows this was a Bad Thing (tm) !

Just to revise, the TTL interconnection rules, one output could drive 7 inputs. Lines had to be driven by special line driver chips. You had to draw 15mA of current out of an input to drag it low, but only microamps to drive it high! Wire OR could only be done with open collector output chip buffers/gates. Then we have to have TRISTATE buffers to have a bus ! Most of my TTL logic board is made from buffer chips (that as every Harvard MBA says, dont add value!). In practice I cannot toggle my flip flops at 30Mhz because I must now add up all the worst case propagation delays in my logic and toggle at 1 or 2 or maybe a breathtaking 5 Mhz if I got my sums right. It got even sillier. An ECL node (read transmission line) is terminated in a resistor that absorbs the unwanted energy of a signal as it bangs into the end of the line. We dont want it coming back, that could make one pulse seem like two or more. The laws of analog transmission lines still apply in the TTL world, we just try to ignore them! At the input of a TTL gate is a reverse biased diode that partially absorbs half of the unwanted energy of a signal pulse and still reflects back towards the source and anybody listening!  When a TTL gate changes state it draws a large and ugly current spike from the supply, which if not carefully decoupled will propagate to a nearby flip flop and changes its state! Thats why its hard to do high speed TTL and easy to do high speed ECL because the analog signals are handled properly.

To be fair and balanced and stuff, TTL did improve, because it had to and because the market said it "sucked".  Then we got HTTL, LSTTL, STTL and CMOS variants for special ultra low power application. The pinnacle was the FTTL seris and the bicmos variants that finally achieved the propagation delays and toggle rates that ECL had twenty years prior.

I had the oppurtunity to perform chip level maintenance on various mainframe and minicomputer systems, DEC, PYRAMID and BURROUGHS. All used mostly or in part TTL.  DEC and PYRAMID all used STTL allmost exclusiveley. The DEC VAX 780 , despite its achitectural elegance was a horrible microprogrammed kludge that despite the "wise" choice of Shottcky TTL could only do a mip. The PYRAMID also used STTL, it was a risc CPU, heavily vertically microprogrammed but it could do 3 or 4 mips. Both machines had a fundamental master clock of 32Mhz divided down to produce a multiphase 8 Mhz system clock.  The chip set in both could have been replaced with ECL equivalents without fundamentally changing the cpu architecture.  The VAX 780 could have run at 50 Mips instead of the lousy 1.0 Mip. The PYRAMID could have rattled its bones at 100 Mips, this in 1980 !

I have recently recieved some very interesting correspondance from  Dr J McMillan of Sheffield about the early history of ECL. Turns out, ECL was a British invention with a heritage going back to the late fifeties!  There is a British patent by Plessey for the basic ecl gate lodged in the early sixties.  The late fifeties reference points to designs for "milli-microsecond transistor current switching circuits".  I suppose I should be hopping mad at this point. The world could have had Cray class machines  in the sixties!