ram-static-tester

Way back in 1987 I was servicing a large mini computer, the Pyramid 90X which as based on 74Sxxx series logic. It was based on a 32Mhz clock divided into 4 phases, and a risc architecture that gave it about 8 MIPS. Built of discrete SSI and MSI devices, the only VLSI devices were the console processor which used a Motorola 68000 and assorted high speed bipolar static RAMS. We did repair these machines to chip level, back then , just swapping boards until it worked was not an option. The CPU was heavily microcoded and came with extensive , very effective diagnostics that ran at both the "cpu" level and at the microcode level. The machine had many caches, instruction buffers, microcode caches, writable control stores implemented with high speed bipolar static rams. In those days, the static ram failure rate was fairly high, Monash University had 6 of these machines at one stage. Diagnosing static ram failures was rendered easy by the microcode diagnostics. They basically told you which chip to change. All well and good, but what if the bad ram was in the writable control store ?

This machine was born of a necessity to bulk checking of machine ram and our small stock of spare ram. Somehow bad ram had found its way into the spares and maybe a third of our spares were suspect. One fine day a Pyramid died with a control store parity so not even diagnostics would run.
So over a weekend I struggled to complete this machine. This machine "mattered" and had been down for a while and the powers that be were not impressed. I had on hand an intel type 2149 that we knew was bad and one 2149 that we thought was good. So with that I wire wrapped away my weekend and by Sunday night it could tell apart good from bad. Why not a microprocessor design ? That would have meant for me a Z80, eprom, static ram, debugger, display and maybe a week of futzing around to get a sign of life. The hard wired design would "just work", as it did.

The core of the design is based on what I call a "Zero Bit Computer". It is a micro sequencer based on a small handful of MSI 74xxx logic. The unique design attribute of the zero bit computer design paradigm is that there exists a one to one isomorphism between a plain natural language description of a sequencing problem and the wiring ( that would be programming) of the zero bit computer. I have discussed this idea in another article in this site. There are two zero bit computers in this design, one does the creation of a chip enable and write enable signals to the static ram under test and it ensures correct setup and hold times of address,data and the WE signal. The other does "gross" sequencing, address generation, write cycle, read back and compare cycle, next data pattern cycle. The machine will write/read/compare ones, zeros , and selection of address bits and halt on error and alarm. It could test 1 bit, 4 bit and 8 bit wide rams with up to 16 address lines.

I built it from discarded mainframe components at zero net cost, this being a university department was a good thing as we had no budget for this kind of playing around.

The machine was wired on these prototype boards that were not prototype boards at all. They were salvaged from redundant Burroughs type BX350 disk pack drive controllers which were mini computers in their own right. Most of the chips are recycled Burroughs mainframe 74xxx seris logic.