A Dynamic RAM testing machine
by Ralph Klimek 1987

based on the principal of the Zero Bit Computer





This machine was designed and biult by me in 1987/8 to demonstrate the Zero Bit Computer concept to myself. There was also a need in our department for the testing of 256kbit dynamic ram chips that were being used in the current generation of PC ATs. This machine permitted rapid go/ no go testing of 64k, 256k and 1Mbit dynamic rams.


Given the slow speed of microprocessors in 1987 it was unrealistic to base a dynamic ram tester on one, especially given the complex timing signals required to make a dynamic ram work. The RAS and CAS signals are also time critical. Only a hardware based sequencer has any prospect of being able to meet the timing requirements of a RAM chip. A Dynamic RAM is only dynamic in the sence that the data representation is in terms of charge stored under the gate electrode of a MOS transistor. This charge is measured in femto coulombs, that is not a lot. A dynamic RAM stores data in the charge stored in this gate capacitance. Data is retained by periodically reading all data and writing it back. The write back is done internally on the chip, the external complexity arises from the requirement to multiplex the address lines using differant sequences to determine the operating mode of the chip. Timing is critical. On writing data, the WE (write enable) signal is not a strobe or clock, it is merely a suggestion to the chip that when the correct RAS CAS sequence occurs, input data is latched internally. To retain data either a special refresh cycle is performed , a sort of dummy read, or just read everything.  Every cell must be read or refreshed every 4 milliseconds.

This machine performs 4 tests,  write /read all one, all zeroes, parity of address bits, inverse parity of address bits.  Using the parity function was a simple way of getting "random data" that was a strong function of the address, this would check that the RAM could properly decode its address bus. This fault could not be flagged by a simple ones and zeroes test.  This machine could cycle continuously where we needed a burn in function.  There is also a mechanism to test access time and this revealed interesting ram behaviour under adverse conditions.





The main sequencing, read write control, done with this microsequencer. Tests included a burn in test, data once written could be read forever untill error.


microsequencer for generating chip RAS and CAS  and clock distribution. The raw RAS and CAS signals from the phase decoders are cleaned up by D flip-flops to eliminate glitches. Note the use of multiple input gates used to create arbitary digital waveforms.



Logical address bits  generator, nothing more than a 20 bit counter. Because of the  long carry propagation delay this counter needed a gated clock rather than run synchronously. Gated clocks break the simple synchronous paradigm but are a requirement when long multi-gate and multi-package have a long serial delay path as the counter carry signal requires. I tried to use look ahead carry but the design effort was beyond me.


data for one bit wide drams was generated by getting the odd and even parity of the address bits and writing that. This gave a reasonably thorough test of the drams ability to decode its address bus.  This tester could measure access time by gating read back data at differant sample times. It revealled that 200ns drams could be run at 100ns if you kept them cold! read back data is compared in the XOR gate. The JK flip flops are clocked on various delayed clock edges and record that state of the data comparison.







logical ram addresses are mapped to physical chip addresses as a function of the chip size


This is the "plain language" microprogram  for both microsequencers. This allmost directly maps to the wiring of the machines. There are two micro programs here. There is the phase sequencer that is responsible for creating the RAS and CAS dram signals and controlling the dram address mux and ensuring the setup and hold time requirement of the dram is satisfied.  The main sequence generator contains the high level program that orchestrates the complete test program.


logic that selects the right address lines to chip address lines for differant sized ram chips. Muxes are used to generate arbitary logic functions, rather than random logic. Errors in design or logic analysis are easily rectified by reallocating ones and zeroes to the mux inputs rather than completely redesigning a random logic map.